MC68HC908GZ8 Datasheet, PDF (43/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Low-Power Modes
Central Processor Unit (CPU)
3.5.2 Stop Mode
Stop mode turns off the COPCLK input to the COP and clears the COP prescaler.
Service the COP immediately before entering or after exiting stop mode to ensure
a full COP timeout period after entering or exiting stop mode.
The STOP bit in the CONFIG1 register enables the STOP instruction. To prevent
inadvertently turning off the COP with a STOP instruction, disable the STOP
instruction by clearing the STOP bit.
3.6 Central Processor Unit (CPU)
3.6.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling
interrupts. After exit from wait mode by interrupt, the I bit remains clear. After
exit by reset, the I bit is set.
• Disables the CPU clock
3.6.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling
external interrupts. After exit from stop mode by external interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
3.7 External Interrupt Module (IRQ)
3.7.1 Wait Mode
The external interrupt (IRQ) module remains active in wait mode. Clearing the
IMASK1 bit in the IRQ status and control register enables IRQ CPU interrupt
requests to bring the MCU out of wait mode.
3.7.2 Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK1 bit in the IRQ
status and control register enables IRQ CPU interrupt requests to bring the MCU
out of stop mode.
MC68HC908GZ8
MOTOROLA
Low-Power Modes
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Data Sheet
43