MC68HC908GZ8 Datasheet, PDF (196/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
MSCAN08 Controller (MSCAN08)
16.13.12 MSCAN08 Identifier Acceptance Registers
On reception each message is written into the background receive buffer. The CPU
is only signalled to read the message, however, if it passes the criteria in the
identifier acceptance and identifier mask registers (accepted); otherwise, the
message will be overwritten by the next message (dropped).
The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3
registers of incoming messages in a bit by bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For
standard identifiers only the first two (CIDMR0/CIDMR1 and CIDAR0/CIDAR1) are
applied.
CIDAR0 Address: $0510
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Reset:
Unaffected by reset
CIDAR1 Address: $050511
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Reset:
CIDAR2 Address: $0512
Bit 7
6
Unaffected by reset
5
4
3
2
1
Bit 0
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Reset:
Unaffected by reset
CIDAR3 Address: $0513
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Reset:
Unaffected by reset
Figure 16-26. Identifier Acceptance Registers
(CIDAR0–CIDAR3)
NOTE:
AC7–AC0 — Acceptance Code Bits
AC7–AC0 comprise a user-defined sequence of bits with which the
corresponding bits of the related identifier register (IDRn) of the receive
message buffer are compared. The result of this comparison is then masked
with the corresponding identifier mask register.
The CIDAR0–CIDAR3 registers can be written only if the SFTRES bit in CMCR0 is
set
Data Sheet
196
MSCAN08 Controller (MSCAN08)
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MC68HC908GZ8
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