MC68HC908GZ8 Datasheet, PDF (203/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Input/Output (I/O) Ports
Port A
NOTE:
DDRA7–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA7–DDRA0, configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
Avoid glitches on port A pins by writing to the port A data register before changing
data direction register A bits from 0 to 1.
Figure 17-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
V_DD
DDRAx
PTAx
PTAPUEx
READ PTA ($0000)
INTERNAL
PULLUP
DEVICE
PTAx
Figure 17-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch.
When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the
pin. The data latch can always be written, regardless of the state of its data
direction bit. Table 17-2 summarizes the operation of the port A pins.
Table 17-2. Port A Pin Functions
PTAPUE
Bit
DDRA
Bit
PTA
Bit
I/O Pin
Mode
1
0
X⁽¹⁾
Input, V_DD(2)
0
0
X
Input, Hi-Z⁽⁴⁾
X
1
X
Output
1. X = Don’t care
2. I/O pin pulled up to V_DD by internal pullup device
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
Accesses
to DDRA
Read/Write
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
Accesses
to PTA
Read
Write
Pin
PTA7–PTA0⁽³⁾
Pin
PTA7–PTA0⁽³⁾
PTA7–PTA0
PTA7–PTA0
MC68HC908GZ8
MOTOROLA
Input/Output (I/O) Ports
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Data Sheet
203