MC68HC908GZ8 Datasheet, PDF (89/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
5. Calculate and verify the adequacy of the VCO and bus frequencies f_VCLK
and f_BUS.
f_VCLK = (N) × f_RCLK
f_BUS = (f_VCLK) ⁄ 4
6. Select the VCO’s power-of-two range multiplier E, according to Table 7-2.
NOTE:
Table 7-2. Power-of-Two Range Selectors
Frequency Range
E
0 < f_VCLK ≤ 8 MHz
0
8 MHz< f_VCLK ≤ 16 MHz
1
16 MHz< f_VCLK ≤ 32 MHz
2⁽¹⁾
1. Do not program E to a value of 3.
7. Select a VCO linear range multiplier, L, where f_NOM = 71.4 kHz
L = Round
f_VCLK
2^E x f_NOM
8. Calculate and verify the adequacy of the VCO programmed center-of-range
frequency, f_VRS. The center-of-range frequency is the midpoint between the
minimum and maximum frequencies attainable by the PLL.
f_VRS = (L x 2^E) f_NOM
9. For proper operation,
f_VRS – f_VCLK
≤
f_{--N----O----M------}×_-----2_---^E_--
2
10. Verify the choice of N, E, and L by comparing f_VCLK to f_VRS and f_VCLKDES.
For proper operation, f_VCLK must be within the application’s tolerance of
f_VCLKDES, and f_VRS must be as close as possible to f_VCLK.
Exceeding the recommended maximum bus frequency or VCO frequency can
crash the MCU.
11. Program the PLL registers accordingly:
a. In the VPR bits of the PLL control register (PCTL), program the binary
equivalent of E.
b. In the PLL multiplier select register low (PMSL) and the PLL multiplier
select register high (PMSH), program the binary equivalent of N. If
using a 1–8 MHz reference, the PMSL register must be reprogrammed
from the reset value before enabling the pll.
c. In the PLL VCO range select register (PMRS), program the binary
coded equivalent of L.
MC68HC908GZ8
MOTOROLA
Clock Generator Module (CGM)
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Data Sheet
89