MC68HC908GZ8 Datasheet, PDF (321/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
I/O Registers
OVERFLOW
OVERFLOW
TCHx
PERIOD
OVERFLOW
OVERFLOW
OVERFLOW
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 23-11. CHxMAX Latency
23.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input
capture function or the output compare value of the output compare function. The
state of the TIM channel registers after reset is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM
channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is
read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM
channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is
written.
Address: T1CH0H, $0026 and T2CH0H, $0031
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
Reset:
Indeterminate after reset
1
Bit 0
9
Bit 8
Figure 23-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 23-13. TIM Channel 0 Register Low (TCH0L)
MC68HC908GZ8
MOTOROLA
Timer Interface Module (TIM)
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Data Sheet
321