MC68HC908GZ8 Datasheet, PDF (74/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
5.8.2.3 Left Justified Signed Data Mode
In left justified signed data mode, the ADRH register holds the eight MSBs of the
10-bit result. The only difference from left justified mode is that the AD9 is
complemented. The ADRL register holds the two LSBs of the 10-bit result. All other
bits read as 0. ADRH and ADRL are updated each time an ADC single channel
conversion completes. Reading ADRH latches the contents of ADRL until ADRL is
read. All subsequent results will be lost until the ADRH and ADRL reads are
completed.
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Write:
Reset:
Unaffected by reset
Address: $003E
Read: AD1
AD0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Unaffected by reset
Figure 5-6. ADC Data Register High (ADRH) and Low (ADRL)
5.8.2.4 Eight Bit Truncation Mode
In 8-bit truncation mode, the ADRL register holds the eight MSBs of the 10-bit
result. The ADRH register is unused and reads as 0. The ADRL register is updated
each time an ADC single channel conversion completes. In 8-bit mode, the ADRL
register contains no interlocking with ADRH.
Address: $003D
ADRH
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
0
0
Write:
Reset:
Unaffected by reset
Address: $003E
ADRL
Read: AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 5-7. ADC Data Register High (ADRH) and Low (ADRL)
Data Sheet
74
Analog-to-Digital Converter (ADC)
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MC68HC908GZ8
MOTOROLA