MC68HC908GZ8 Datasheet, PDF (138/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
External Interrupt (IRQ)
To protect CPU interrupt flags during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status
and control register during the break state has no effect on the IRQ interrupt flags.
12.6 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors operation of
the IRQ module. The INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Address:
Read:
Write:
Reset:
$001D
Bit 7
6
5
4
3
2
1
IRQF
0
IMASK
ACK
0
0
0
0
0
0
0
= Unimplemented
Figure 12-3. IRQ Status and Control Register (INTSCR)
Bit 0
MODE
0
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as
logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset
clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears
MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
Data Sheet
138
External Interrupt (IRQ)
For More Information On This Product,
Go to: www.freescale.com
MC68HC908GZ8
MOTOROLA