MC68HC908GZ8 Datasheet, PDF (284/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
The transmit data buffer allows back-to-back transmissions without the slave
precisely timing its writes between transmissions as in a system with a single data
buffer. Also, if no new data is written to the data buffer, the last value contained in
the shift register is the next data word to be transmitted.
For an idle master or idle slave that has no data loaded into its transmit buffer, the
SPTE is set again no more than two bus cycles after the transmit buffer empties
into the shift register. This allows the user to queue up a 16-bit value to send. For
an already active slave, the load of the shift register cannot occur until the
transmission is completed. This implies that a back-to-back write to the transmit
data register is not possible. The SPTE indicates when the next write can occur.
21.7 Error Conditions
The following flags signal SPI error conditions:
• Overflow (OVRF) — Failing to read the SPI data register before the next full
byte enters the shift register sets the OVRF bit. The new byte does not
transfer to the receive data register, and the unread byte still can be read.
OVRF is in the SPI status and control register.
• Mode fault error (MODF) — The MODF bit indicates that the voltage on the
slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in
the SPI status and control register.
21.7.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still has unread
data from a previous transmission when the capture strobe of bit 1 of the next
transmission occurs. The bit 1 capture strobe occurs in the middle of SPSCK cycle
7 (see Figure 21-4 and Figure 21-6.) If an overflow occurs, all data received after
the overflow and before the OVRF bit is cleared does not transfer to the receive
data register and does not set the SPI receiver full bit (SPRF). The unread data that
transferred to the receive data register before the overflow occurred can still be
read. Therefore, an overflow error always indicates the loss of data. Clear the
overflow flag by reading the SPI status and control register and then reading the
SPI data register.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable
bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same
CPU interrupt vector (see Figure 21-11.) It is not possible to enable MODF or
OVRF individually to generate a receiver/error CPU interrupt request. However,
leaving MODFEN low prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an
overflow condition. Figure 21-9 shows how it is possible to miss an overflow. The
first part of Figure 21-9 shows how it is possible to read the SPSCR and SPDR to
clear the SPRF without problems. However, as illustrated by the second
transmission example, the OVRF bit can be set in between the time that SPSCR
and SPDR are read.
Data Sheet
284
Serial Peripheral Interface (SPI) Module
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MC68HC908GZ8
MOTOROLA