MC68HC908GZ8 Datasheet, PDF (187/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
MSCAN08 Controller (MSCAN08)
Programmer’s Model of Control Registers
NOTE:
WUPM — Wakeup Mode
This flag defines whether the integrated low-pass filter is applied to protect the
MSCAN08 from spurious wakeups (see 16.8.5 Programmable Wakeup
Function).
1 = MSCAN08 will wakeup the CPU only in cases of a dominant pulse on the
bus which has a length of at least t_wup.
0 = MSCAN08 will wakeup the CPU after any recessive-to-dominant edge on
the CAN bus.
CLKSRC — Clock Source
This flag defines which clock source the MSCAN08 module is driven from (see
16.10 Clock System).
1 = The MSCAN08 clock source is CGMOUT (see Figure 16-7).
0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 16-7).
The CMCR1 register can be written only if the SFTRES bit in the MSCAN08
module control register is set
16.13.3 MSCAN08 Bus Timing Register 0
Address:
Read:
Write:
Reset:
$0502
Bit 7
6
5
4
3
2
1
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
0
0
0
0
0
0
0
Figure 16-17. Bus Timing Register 0 (CBTR0)
Bit 0
BRP0
0
SJW1 and SJW0 — Synchronization Jump Width
The synchronization jump width (SJW) defines the maximum number of time
quanta (T_q) clock cycles by which a bit may be shortened, or lengthened, to
achieve resynchronization on data transitions on the bus (see Table 16-6).
SJW1
0
0
1
1
Table 16-6. Synchronization Jump Width
SJW0
0
1
0
1
Synchronization Jump Width
1 T_q cycle
2 T_q cycle
3 T_q cycle
4 T_q cycle
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (T_q) clock, which is used to build up the
individual bit timing, according to Table 16-7.
MC68HC908GZ8
MOTOROLA
MSCAN08 Controller (MSCAN08)
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Data Sheet
187