MC68HC908GZ8 Datasheet, PDF (261/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Reset and System Initialization
OSC1
PORRST
CGMXCLK
4096
CYCLES
32
CYCLES
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 20-7. POR Recovery
20.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP
counter causes an internal reset and sets the COP bit in the SIM reset status
register (SRSR). The SIM actively pulls down the RST pin for all internal reset
sources.
The COP module is disabled if the RST pin or the IRQ pin is held at V_TST while the
MCU is in monitor mode. The COP module can be disabled only through
combinational logic conditioned with the high voltage signal on the RST or the IRQ
pin. This prevents the COP from becoming disabled as a result of external noise.
During a break state, V_TST on the RST pin disables the COP module.
20.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal
instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a
reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats
the STOP instruction as an illegal opcode and causes an illegal opcode reset. The
SIM actively pulls down the RST pin for all internal reset sources.
20.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset.
The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit
in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from
an unmapped address does not generate a reset. The SIM actively pulls down the
RST pin for all internal reset sources.
MC68HC908GZ8
MOTOROLA
System Integration Module (SIM)
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Data Sheet
261