MC68HC908GZ8 Datasheet, PDF (75/344 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
I/O Registers
5.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
R
Write:
Reset: 0
0
0
0
0
1
0
0
= Unimplemented
R
= Reserved
Figure 5-8. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC
to generate the internal ADC clock. Table 5-2 shows the available clock
configurations. The ADC clock should be set to approximately 1 MHz.
Table 5-2. ADC Clock Divide Ratio
ADIV2
ADIV1
0
0
0
0
0
1
0
1
1
X⁽¹⁾
1. X = Don’t care
ADIV0
0
1
0
1
X⁽¹⁾
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK)
as the input clock source to generate the internal ADC clock. Reset selects
CGMXCLK as the ADC clock source.
1 = Internal bus clock
0 = Oscillator output clock (CGMXCLK)
The ADC requires a clock rate of approximately 1 MHz for correct operation. If the
selected clock source is not fast enough, the ADC will generate incorrect
conversions. See 24.10 5.0-Volt ADC Characteristics.
f_ADIC =
f_CGMXCLK or bus frequency _{≅ 1 MHz}
ADIV[2:0]
MC68HC908GZ8
MOTOROLA
Analog-to-Digital Converter (ADC)
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Data Sheet
75