M306V2ME Datasheet, PDF (43/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.5.7 Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 2.5.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. The following shows the operational modes of internal
clock φ.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. Note that oscillation of the main clock must have
stabilized before transferring from this mode to another mode.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is used as the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized
before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after
the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized
immediately after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note: When switching the count source for BCLK between XIN and XCIN, it needs that the oscillation of
the switched count source is sufficiently stable. Shift after taking the oscillation stabilizing time by
software.
Table 2.5.4 Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
Operating mode of BCLK
0
1
0
0
0
Invalid Division by 2 mode
1
0
0
0
0
Invalid Division by 4 mode
Invalid Invalid
0
1
0
Invalid Division by 8 mode
1
1
0
0
0
Invalid Division by 16 mode
0
0
0
0
0
Invalid No-division mode
Invalid Invalid
1
Invalid
0
1
Low-speed mode
Invalid Invalid
1
Invalid
1
1
Low power dissipation mode
Rev. 1.0
43