M306V2ME Datasheet, PDF(133/276 Page) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER　

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M306V2ME Datasheet, PDF (133/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER　

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MITSUBISHI MICROCOMPUTERS

M306V2ME-XXXFP

M306V2EEFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

(2) I2Ci data shift register, I2Ci transmit buffer register (i = 0, 1)

The I2Ci data shift register is an 8-bit shift register to store receive data and write transmit data.

When transmit data is written into this register, it is transferred to the outside from bit 7 in synchroniza-

tion with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit

to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL

clock, and each time one-bit data is input, the data of this register are shifted one bit to the left.

The I2Ci data shift register is in a write enable status only when the ESO bit of the I2Ci control register

is â1.â The bit counter is reset by a write instruction to the I2Ci data shift register. When both the ESO

bit and the MST bit of the I2Ci status register are â1,â the SCL is output by a write instruction to the I2Ci

data shift register. Reading data from the I2Ci data shift register is always enabled regardless of the

ESO bit value.

The I2Ci transmit buffer register is a register to store transmit data (slave address) to the I2Ci data shift

register before RESTART condition generation. That is, in master, transmit data written to the I2Ci

transmit buffer register is written to the I2Ci data shift register simultaneously. However, the SCL is not

output. The I2Ci transmit buffer register can be written only when the ESO bit is â1,â reading data from

the I2Ci transmit buffer register is disabled regardless of the ESO bit value.

Notes 1: To write data into the I2Ci data shift register or the I2Ci transmit buffer register after the MST

bit value changes from â1â to â0â (slave mode), keep an interval of 20 BCLK or more.

2: To generate START/RESTART condition after the I2Ci data shift register or the I2Ci transmit

buffer register is written, keep an interval of 2 BCLK or more.

Rev. 1.0

133

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