M306V2ME Datasheet, PDF (186/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC).
At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising
edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So
interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs
enough time (2 ! BCLK cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can
select with the I/O polarity control register (address 020616).
8 ! BCLK cycles or more
VSYNC signal input
VSYNC control
signal in
microcomputer
Period of counting
HSYNC signal
HSYNC
signal input
26 ! BCLK cycles
or more
0.1 to 0.2 [µs]
(BCLK = 10 MHz)
(Note 2)
12345
Not count
When bits 0 and 1 of the I/O polarity control register
(address 020616) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of
HSYNC signal after rising edge of VSYNC control signal in the
microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of HSYNC needs 26 ! BCLK cycles or more
(BCLK = 10 MHz).
Figure 2.16.9 Supplement explanation for display position
Rev. 1.0
186