M306V2ME Datasheet, PDF (148/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
s START condition generating procedure using multi-master
:
FCLR
I
(Interrupt disabled)
BTST
5, IICiS1
(BB flag confirming and branch process)
JC
BUSBUSY
BUSFREE:
MOV.B SA, IICiS0
(Writing of slave address value <SA>)
NOP
NOP
Œ
MOV.B
#F0H, IICiS1
(Trigger of START condition generating)
FSET
I
(Interrupt enabled)
:
BUSBUSY:
FSETI
(Interrupt enabled)
:
ΠBe sure to add NOP instruction ! 2 between writing the slave address value and setting trigger of
START condition generating shown the above procedure example.
 When using multi-master system, disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts immediately.
When using single-master system, it is not necessary to disable interrupts above.
s RESTART condition generating procedure
:
MOV.B SA, IICiS0S
(Writing of slave address value <SA>)
Œ
NOP
NOP
MOV.B #F0H, IICiS1
(Trigger of RESTART condition generating)
:
Œ Use the I²Ci transmit buffer register to write the slave address value to the I²Ci data shift register.
And also, be sure to add NOP instruction ! 2.
s Writing to I²Ci status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released
and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the
MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become
the same as above.
s Process of after STOP condition generating
Do not write data in the I²Ci data shift register (IICiS0) and the I²Ci status register (IICiS1) until the bus
busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the
STOP condition waveform might not be normally generated. Reading to the above registers do not have
the problem.
Rev. 1.0
148