M306V2ME Datasheet, PDF (136/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(4) I²Ci clock control register (i = 0, 1)
The I²Ci clock control register is used to set ACK control, SCL mode and SCL frequency.
s Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency.
s Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the
bit is set to “1,” the high-speed clock mode is set.
s Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock^V is generated. When this bit is set to “0,” the ACK
return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK
clock.
However, when the slave address matches the address data in the reception of address data at ACK
BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made HIGH (ACK is not returned).
VACK clock: Clock for acknowledgement
s Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmis-
sion. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after
data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an
ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data
and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives
the ACK bit generated by the data receiving device.
Note: Do not write data into the I²Ci clock control register during transmission. If data is written during
transmission, the I²Ci clock generator is reset, so that data cannot be transmitted normally.
Rev. 1.0
136