M306V2ME Datasheet, PDF (257/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 5.8.2 Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
(referenced to VCC = 5 V, VSS = 0 V at Ta = 25 ^oC, CM15 = “1” unless otherwise specified)
Symbol
Parameter
Measuring condition ^Standard
Min. Max.
Unit
td(BCLK-AD) Address output delay time
35
ns
th(BCLK-AD) Address output hold time (BCLK standard)
4
ns
th(RD-AD)
Address output hold time (RD standard)
0
ns
th(WR-AD)
Address output hold time (WR standard)
0
ns
td(BCLK-CS) Chip select output delay time
35
ns
th(BCLK-CS) Chip select output hold time (BCLK standard)
4
ns
td(BCLK-ALE)
th(BCLK-ALE)
ALE signal output delay time
ALE signal output hold time
35
ns
Figure 5.9.1
–4
ns
td(BCLK-RD) RD signal output delay time
35
ns
th(BCLK-RD) RD signal output hold time
0
ns
td(BCLK-WR) WR signal output delay time
35
ns
th(BCLK-WR) WR signal output hold time
0
ns
td(BCLK-DB) Data output delay time (BCLK standard)
40
ns
th(BCLK-DB) Data output hold time (BCLK standard)
4
ns
td(DB-WR)
Data output delay time (WR standard)
(Note 1)
ns
th(WR-DB)
Data output hold time (WR standard)(Note 2)
0
ns
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
10 ⁹
f(BCLK) ^{– 40} [ns]
2: This is standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
R
Hold time of data bus is expressed in
t = –CR ! ln (1 – VOL / VCC)
DBi
by a circuit of the right figure.
C
For example, when VOL = 0.2VCC, C = 30 pF, R = 1 kΩ, hold time
of output “L” level is
t = – 30 pF ! 1kΩ ! ln (1 – 0.2VCC / VCC)
= 6.7 ns.
Rev. 1.0
257