M306V2ME Datasheet, PDF (176/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.15 HSYNC Counter
The synchronous signal counter counts HSYNC from HSYNC count input pins (HC0/P75, HC1/P77) as a
count source.
The count value in a certain time (T time; 1024 µs, 2048 µs, 4096 µs and 8192 µs) divided system clock f 32
is stored into the 8-bit latch.
Accordingly, the latch value changes in the cycle of T time. When the count value exceeds “FF16,” “FF16”
is stored into the latch.
The latch value can be obtained by reading out the HSYNC counter latch (address 027F16). A count source
and count update cycle (T time) are selected by bits 0, 3 and 4 of the HSYNC counter register.
Figure 2.15.1 shows the HSYNC counter and Figure 2.15.2 shows the synchronous signal counter block
diagram.
Note: When using the HSYNC counter, set bit 7 of the peripheral mode register (address 027D16) according
to the main clock frequency.
HSYNC counter register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
HC
Address
026716
When reset
XXX00X0016
Bit symbol
Bit name
HCC0 Count source switch bit
Function
0 : HC0/P75 pin input
1 : HC1/P77 pin input
RW
HCC1 ^{Input polarity}
switch bit
0:
1 : ^{(Falling edge count)}
(Rising edge count)
Nothing is assigned. In an attempt to write to this bit, write “0.”
The value, if read, turns out to be “0.”
HCC3 Count freguency
selection bits
HCC4
b4 b3 <Count freguency>
0 0 : 1024 µs
0 1 : 2048 µs
1 0 : 4096 µs
1 1 : 8192 µs
Nothing is assigned. In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
Note: When HC0 and HC1 input are positive polarity (negetive polarity),
HIGH width (LOW width) needs 3 main clock cycles or more of system clock.
Figure 2.15.1 HSYNC counter register
System clock f32
HC0/P75
HC1/P77
1024 µs
Freguency divider
2048 µs
4096 µs
8192 µs
HCC1
Polarity switch
HCC0
Selection gate : connected to black
side when reset.
Figure 2.15.2 HSYNC counter block diagram
HCC3, HCC4
Reset
8-bit counter
Latch (8 bits)
Counter
HSYNC
counter latch
Data bus
Rev. 1.0
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