M306V2ME Datasheet, PDF (169/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.14.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video signal input from the CVIN pin. The low-
pass filter attenuates the noise of clamped composite video signal. The CVIN pin to which composite video
signal is input requires a capacitor (0.1 mF) coupling outside. Pull down the CVIN pin with a resistor of
hundreds of kiloohms to 1 MΩ. In addition, we recommend to install externally a simple low-pass filter
using a resistor and a capacitor at the CVIN pin (refer to Figure 2.14.1).
2.14.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal of the low-pass filter.
2.14.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the compos-
ite sync signal taken out in the sync slice circuit.
(1) Horizontal synchronous signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync
signal.
(2) Vertical synchronous signal (Vsep)
As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit
4 of the data slicer control register 2 (address 026116).
•Method 1 The “L” level width of the composite sync signal is measured. If this width exceeds a
certain time, a Vsep signal is generated in synchronization with the rising of the timing
signal immediately after this “L” level.
•Method 2 The “L” level width of the composite sync signal is measured. If this width exceeds a
certain time, it is detected whether a falling of the composite sync signal exits or not in the
“L” level period of the timing signal immediately after this “L” level. If a falling exists, a Vsep
signal is generated in synchronization with the rising of the timing signal (refer to Figure
2.14.6).
Figure 2.14.6 shows a Vsep generating timing. The timing signal shown in the figure is generated from the
reference clock which the timing generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the
composite sync signal. As shown in Figure 2.14.7, when the A level matches the B level, this bit is “0.” In
the case of a mismatch, the bit is “1.”
Composite s
Timing
signal
Measure “L” period
Vsep signal
A Vsep signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
Figure 2.14.6 Vsep generating timing (method 2)
Rev. 1.0
169