M306V2ME Datasheet, PDF (34/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting
the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK
cycle. When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcom-
puter has been reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two
or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set
this bit after referring to the recommended operating conditions (main clock input oscillation fre-
________
quency) of the electric characteristics. However, when the user is using the RDY signal, the relevant
bit in the chip select control register’s bits 4 to 7 must be set to “0.”
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______
_______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed
in one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset. These bits default to “0” after the microcomputer
has been reset.
The SFR area and the OSD RAM area are always accessed in two BCLK cycles regardless of the
setting of these control bits. Also, the corresponding bits of the chip select control register must be set
to “0” if using the multiplex bus to access the external memory area.
Table 2.4.9 shows the software wait and bus cycles. Figure 2.4.8 shows example bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the
protect register (address 000A16) to “1”.
Table 2.4.9 Software waits and bus cycles
Area
SFR/
OSD RAM
Internal
ROM/RAM
Bus status
Wait bit
Invalid
0
1
Bits 4 to 7 of chip select
control register
Invalid
Invalid
Invalid
Separate bus
0
1
Separate bus
0
External
memory
Separate bus
1
area
Multiplex bus
0
0
0 (Note)
0
Multiplex bus
1
Note: When using the RDY signal, always set to “0.”
0 (Note)
Bus cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
34
Rev. 1.0