M306V2ME Datasheet, PDF (264/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Read timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
RD
td(BCLK–CS)
tcyc
35ns.max
td(AD–ALE)
th(ALE–AD)
(tcyc/2-25)ns.min 30ns.min
Address
td(BCLK–AD)
35ns.max
tdz(RD–AD)
8ns.max
tac3(RD–DB)
td(AD–RD)
0ns.min
td(BCLK–ALE)
35ns.max
th(BCLK–ALE)
–4ns.min
td(BCLK–RD)
35ns.max
th(RD–CS)
(tcyc/2)ns.min
th(BCLK–CS)
4ns.min
Data input
tSU(DB–RD)
40ns.min
th(RD–DB)
0ns.min
Address
th(BCLK–AD)
4ns.min
th(RD–AD)
(tcyc/2)ns.min
th(BCLK–RD)
0ns.min
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR,WRL,
WRH
td(BCLK–CS)
tcyc
35ns.max
Address
td(AD–ALE)
(tcyc/2–25)ns.min
td(BCLK–AD)
35ns.max
td(BCLK–DB)
40ns.max
Data output
td(DB–WR)
(tcyc*3/2–40)ns.min
td(BCLK–ALE)
35ns.max
th(BCLK–ALE)
–4ns.min
td(AD–WR)
0ns.min
td(BCLK–WR)
35ns.max
th(WR–CS)
(tcyc/2)ns.min
th(BCLK–CS)
4ns.min
th(WR–DB)
(tcyc/2)ns.min
th(BCLK–DB)
4ns.min
Address
th(BCLK–AD)
4ns.min
th(WR–AD)
(tcyc/2)ns.min
th(BCLK–WR)
0ns.min
Measuring conditions
• VCC=5V
• Input timing voltage : Determined with VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with V OL=0.8V, VOH=2.0V
Figure 5.10.5 Timing diagram in memory expansion mode and microprocessor mode (4)
Rev. 1.0
264