M306V2ME Datasheet, PDF (28/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
In memory expansion mode, select a 8-bit multiplex bus.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed
bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256
bytes can be used in each chip select.
Table 2.4.2 Pin functions for each processor mode
Processor mode
Single-chip
mode
Memory expansion mode/microprocessor modes
Multiplexed bus
space select bit
“01”, “10”
Either CS1 or CS2 is for
multiplexed bus and others
are for separate bus
“00”
(separate bus)
Data bus width
BYTE pin level
P00 to P07
I/O port
8 bits
= “H”
Data bus
16 bits
= “L”
Data bus
8 bits
= “H”
Data bus
16 bits
= “L”
Data bus
Memory
expansion mode
“11” (Note 1)
Multiplexed
bus for the
entire
space
8 bits
= “H”
I/O port
P10 to P17
P 20
P21 to P27
P 30
P31 to P37
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port
Address bus
Address bus Address bus Address bus
/data bus(Note 3)
Address bus
Address bus
Address bus Address bus
/data bus(Note 3) /data bus(Note 3)
Address bus Address bus
/data bus(Note 3)
Address bus Address bus
Address bus Address bus Address bus Address bus
Address bus
/data bus
Address bus
/data bus
A8/D7
I/O port
P40 to P43
Port P40 to P43
function select bit = 1
P40 to P43
Port P40 to P43
function select bit = 0
P44 to P47
I/O port
I/O port
I/O port
P50 to P53
I/O port
P 54
I/O port
P 55
I/O port
P 56
I/O port
I/O port
I/O port
/O port
I/O port
I/O port
Address bus Address bus Address bus Address bus I/O port
CS (chip select) or programmable I/O port
(For details, refer to “2.4.4 Bus control”)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “2.4.4 Bus control”)
HLDA
HLDA
HLDA
HLDA
HLDA
HOLD
HOLD
HOLD
HOLD
HOLD
ALE
ALE
ALE
ALE
ALE
P 57
I/O port
RDY
RDY
RDY
RDY
RDY
Notes 1: In memory expansion mode, select a 8-bit multiplex bus.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be
chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be
used in each chip select.
2: Address bus when in separate bus mode.
Rev. 1.0
28