M306V2ME Datasheet, PDF (171/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.14.6 Data Slice Line Specification Circuit
(1) Specification of data slice line
This circuit decides a line on which caption data is superimposed. The line 21 (fixed), 1 appropriate
line for a period of 1 field (total 2 line for a period of 1 field), and both fields (F1 and F2) are sliced their
data. The caption position register (address 026616) is used for each setting (refer to Table 2.14.1).
The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the
counter value matched the value specified by bits 4 to 0 of the caption position register, this Hsep is
sliced.
The values of “0016” to “1F16” can be set in the caption position register (at setting only 1 appropriate
line). Figure 2.14.8 shows the signals in the vertical blanking interval. Figure 2.14.9 shows the caption
position register.
(2) Specification of line to set slice voltage
The reference voltage for slicing (slice voltage) is generated for the clock run-in pulse in the particular
line (refer to Table 2.14.1). The field to generate slice voltage is specified by bit 1 of data slicer control
register 1. The line to generate slice voltage 1 field is specified by bits 6, 7 of the caption position
register (refer to Table 2.14.1).
(3) Field determination
The field determination flag can be read out by bit 3 of data slicer control register 2. This flag change
at the falling edge of Vsep.
Video signal
Composite video
signal
Vsep
Hsep
Vertical blanking interval
1 appropriate line is set by
the caption position register
(when setting line 19)
Line 21
Count value to be set in the caption position register (“0F16” in this case)
Magnified drawing
Hsep
Composite video
signal
Window for
deteminating
clock-run-in
Clock run-in
Start bit + 16-bit data
Start bit
Figure 2.14.8 Signals in vertical blanking interval
Rev. 1.0
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