M306V2ME Datasheet, PDF (175/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.14.12 Interrupt Request Generating Circuit
The interrupt requests as shown in Table 2.14.3 are generated by combination of the following bits; bits 6
and 7 of the caption position register (address 026616). Read out the contents of data registers 1, 2 and
the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt
request.
Table 2.14.2 Contents of caption data latch completion flag and 16-bit shift register
Slice Line Specification Mode Contents of Caption Data Latch Completion Flag
Contents of 16-bit Shift Register
CPS
bit 7
bit 6
Completion Flag 1 Completion Flag 2
(bit 0 of DSC2)
(bit 5 of CPS)
Caption Data
Register 1
Caption Data
Register 2
0
0
Line 21
A line specified by
bits 4 to 0 of CPS
16-bit data of line 21
16-bit data of a line specified
by bits 4 to 0 of CPS
0
1
A line specified by
bits 4 to 0 of CPS
Invalid
16-bit data of a line specified
by bits 4 to 0 of CPS
Invalid
1
0
Line 21
Invalid
16-bit data of line 21
Invalid
1
1
CPS: Caption position register
DSC2: Data slicer control register 2
Line 21
A line specified by
bits 4 to 0 of CPS
16-bit data of line 21
16-bit data of a line specified
by bits 4 to 0 of CPS
Table 2.14.3 Occurrence sources of Interrupt request
CPS
b7
b6
0
0
1
0
1
1
Occurrence Sources of Interrupt Request at End of Data Slice Line
After slicing line 21
After a line specified by bits 4 to 0 of CPS
After slicing line 21
After slicing line 21
CPS: Caption position register
Data slicer reserved register i (i =1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 00 0
Symbol
DR1
DR2
Address
026816
026716
When reset
0016
0016
Bit symbol
Reserved bits
Bit name
Description
Mest always be set to “0”
Figure 2.14.12 Data slicer reserved register i (i = 1, 2)
RW
Rev. 1.0
175