M306V2ME Datasheet, PDF (258/276 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 5.8.3 Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
(referenced to VCC = 5 V, VSS = 0 V at Ta = 25 ^oC, CM15 = “1” unless otherwise specified)
Symbol
Parameter
Measuring condition
td(BCLK-AD) Address output delay time
th(BCLK-AD) Address output hold time (BCLK standard)
th(RD-AD)
Address output hold time (RD standard)
th(WR-AD) Address output hold time (WR standard)
td(BCLK-CS)
th(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
th(RD-CS)
Chip select output hold time (RD standard)
th(WR-CS) Chip select output hold time (WR standard)
td(BCLK-RD) RD signal output delay time
th(BCLK-RD) RD signal output hold time
td(BCLK-WR) WR signal output delay time
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Figure 5.9.1
td(DB-WR) Data output delay time (WR standard)
th(WR-DB) Data output hold time (WR standard)
td(BCLK-ALE) ALE signal output delay time (BCLK standard)
th(BCLK-ALE) ALE signal output hold time (BCLK standard)
td(AD-ALE) ALE signal output delay time (Address standard)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdZ(RD-AD)
ALE signal output hold time (Adderss standard)
Post-address RD signal output delay time
Post-address WR signal output delay time
Address output floating start time
Note: Calculated according to the BCLK frequency as follows:
10⁹
th(RD – AD) =
f(BCLK) ! 2
[ns]
10 ⁹
th(WR – AD) =
f(BCLK) ! 2
[ns]
Standard
Min. Max.
35
4
(Note)
(Note)
35
4
(Note)
(Note)
35
0
35
0
40
4
(Note)
(Note)
35
–4
(Note)
30
0
0
8
10 ⁹
th(RD – CS) =
f(BCLK) ! 2
[ns]
10 ⁹
th(WR – CS) =
f(BCLK) ! 2
[ns]
td(DB – WR) =
10 ⁹ ! 3 _{– 40}
f(BCLK) ! 2
[ns]
10 ⁹
th(WR – DB) =
f(BCLK) ! 2
[ns]
10 ⁹
td(AD – ALE) =
– 25
f(BCLK) ~2
[ns]
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 1.0
258