PIC18F4539 Datasheet, PDF (98/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
9.6 Parallel Slave Port
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC18F4X39).
PORTD also operates as an 8-bit wide Parallel Slave
Port, or microprocessor port, when control bit
PSPMODE (TRISE<4>) is set. It is asynchronously
readable and writable by the external world through RD
control input pin, RE0/AN5/RD and WR control input
pin, RE1/AN6/WR.
The PSP can directly interface to an 8-bit microproces-
sor data bus. The external microprocessor can read or
write the PORTD latch as an 8-bit latch. Setting bit
PSPMODE enables port pin RE0/AN5/RD to be the RD
input, RE1/AN6/WR to be the WR input and RE2/AN7/
CS to be the CS (chip select) input. For this functional-
ity, the corresponding data direction bits of the TRISE
register (TRISE<2:0>) must be configured as inputs
(set). The A/D port configuration bits, PCFG2:PCFG0
(ADCON1<2:0>), must be set, which will configure pins
RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>)
is set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O.
In this mode, the input buffers are TTL.
FIGURE 9-10:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
Data Bus
DQ
WR LATD
or
PORTD
CK
Data Latch
Q
D
RD PORTD
ENEN
TRIS Latch
RDx
Pin
TTL
RD LATD
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read _TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 9-11:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
DS30485A-page 96
Preliminary
 2002 Microchip Technology Inc.