PIC18F4539 Datasheet, PDF (95/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

9.5 PORTE, TRISE and LATE
Registers
This section is only applicable to the PIC18F4X39
devices.
PORTE is a 3-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register reads and writes the latched output value for
PORTE.
PORTE has three pins (RE0/AN5/RD, RE1/AN6/WR
and RE2/AN7/CS) which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
Register 9-1 shows the TRISE register, which also
controls the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as '0's.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note: On a Power-on Reset, these pins are
configured as analog inputs.
EXAMPLE 9-5: INITIALIZING PORTE
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTE
LATE
0x07
ADCON1
0x05
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
PIC18FXX39
FIGURE 9-9:
PORTE BLOCK DIAGRAM
IN I/O PORT MODE
RD LATE
Data
Bus
WR LATE
or PORTE
DQ
CK
Data Latch
DQ
WR TRISE
CK
TRIS Latch
RD TRISE
I/O pin⁽¹⁾
Schmitt
Trigger
Input
Buffer
RD PORTE
To Analog Converter
Q
D
ENEN
Note 1: I/O pins have diode protection to VDD and VSS.
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 93