PIC18F4539 Datasheet, PDF (285/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
TABLE 23-18: MASTER SSP I²C BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) —
ms
400 kHz mode 2(TOSC)(BRG + 1) —
ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
101 TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) —
ms
400 kHz mode 2(TOSC)(BRG + 1) —
ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
102 TR
SDA and SCL
rise time
100 kHz mode
400 kHz mode
—
20 + 0.1 CB
1000
300
ns CB is specified to be from
ns ^{10 to 400 pF}
1 MHz mode⁽¹⁾
—
300 ns
103 TF
SDA and SCL
fall time
100 kHz mode
400 kHz mode
—
20 + 0.1 CB
1000
300
ns VDD ≥ 4.2V
ns VDD ≥ 4.2V
90
TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) —
ms Only relevant for
setup time
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms ^{Repeated START}
ms ^condition
91
THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) —
ms After this period, the first
hold time
400 kHz mode 2(TOSC)(BRG + 1) —
ms ^{clock pulse is generated}
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
106 THD:DAT Data input
hold time
100 kHz mode
400 kHz mode
0
—
ns
0
0.9 ms
107 TSU:DAT Data input
100 kHz mode
250
—
ns (Note 2)
setup time
400 kHz mode
100
—
ns
92
TSU:STO STOP condition 100 kHz mode 2(TOSC)(BRG + 1) —
ms
setup time
400 kHz mode 2(TOSC)(BRG + 1) —
ms
1 MHz mode⁽¹⁾ 2(TOSC)(BRG + 1) —
ms
109 TAA
Output valid from 100 kHz mode
clock
400 kHz mode
—
3500 ns
—
1000 ns
1 MHz mode⁽¹⁾
—
—
ns
110 TBUF Bus free time 100 kHz mode
4.7
— ms Time the bus must be free
400 kHz mode
1.3
—
ms ^{before a new transmission}
can start
D102 CB
Bus capacitive loading
—
400 pF
Note 1: Maximum pin capacitance = 10 pF for all I²C pins.
2: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line
is released.
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 283