PIC18F4539 Datasheet, PDF (12/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
FIGURE 1-2:
PIC18F4X39 BLOCK DIAGRAM
Data Bus<8>
21
Address Latch
Program Memory
(up to 2 Mbytes)
Data Latch
16
21 ^{Table Pointer}
inc/dec logic
88
8
21
PCLATU PCLATH
PCU PCH PCL
Program Counter
31 Level Stack
Data Latch
Data RAM
(up to 4K
address reach)
Address Latch
12 ⁽²⁾
Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Bank0, F
12
Table Latch
8
ROM Latch
Decode
inc/dec
logic
OSC2/CLKO
OSC1/CLKI
T1OSCI
T1OSCO
MCLR
VDD, VSS
Instruction
Decode &
Control
Timing
Generation
4X PLL
Precision
Voltage
Reference
Instruction
Register
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Low Voltage
Programming
In-Circuit
Debugger
8
PRODH PRODL
3
8 x 8 Multiply
8
BIT OP
8
WREG
8
8
8
ALU<8>
8
PORTA
PORTB
PORTC
PORTD
PORTE
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
RB0/INT0
RB1/INT1
RB2/INT2
RB3
RB4
RB5/PGM
RB6/PGC
RB7/PGD
RC0/T13CKI
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
PWM1
PWM2
Timer0
Timer1
Timer2
Timer3
A/D Converter
PWM1
PWM2
Master
Synchronous
Serial Port
Addressable
USART
Parallel Slave Port
Data EEPROM
Note
1: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
2: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
DS30485A-page 10
Preliminary
 2002 Microchip Technology Inc.