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| PIC18F4539 Datasheet, PDF (28/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel | |||
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PIC18FXX39
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
TOSH
TOSL
STKPTR
2439 4439 2539 4539
2439 4439 2539 4539
2439 4439 2539 4539
2439 4439 2539 4539
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
uu-u uuuu(1)
PCLATU
2439 4439 2539 4539
---0 0000
---0 0000
---u uuuu
PCLATH
PCL
2439 4439 2539 4539
2439 4439 2539 4539
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PC + 2(2)
TBLPTRU 2439 4439 2539 4539
--00 0000
--00 0000
--uu uuuu
TBLPTRH 2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
TBLPTRL 2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
TABLAT
2439 4439 2539 4539
0000 0000
0000 0000
uuuu uuuu
PRODH
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
INTCON
INTCON2
INTCON3
2439 4439 2539 4539
2439 4439 2539 4539
2439 4439 2539 4539
2439 4439 2539 4539
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
uuuu uuuu
uuuu uuuu(3)
uuuu -u-u(3)
uu-u u-uu(3)
INDF0
2439 4439 2539 4539
N/A
N/A
N/A
POSTINC0 2439 4439 2539 4539
N/A
N/A
N/A
POSTDEC0 2439 4439 2539 4539
N/A
N/A
N/A
PREINC0 2439 4439 2539 4539
N/A
N/A
N/A
PLUSW0
2439 4439 2539 4539
N/A
N/A
N/A
FSR0H
2439 4439 2539 4539
---- xxxx
---- uuuu
---- uuuu
FSR0L
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
2439 4439 2539 4539
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
2439 4439 2539 4539
N/A
N/A
N/A
POSTINC1 2439 4439 2539 4539
N/A
N/A
N/A
POSTDEC1 2439 4439 2539 4539
N/A
N/A
N/A
PREINC1 2439 4439 2539 4539
N/A
N/A
N/A
PLUSW1
2439 4439 2539 4539
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits
are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read â0â.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read â0â.
DS30485A-page 26
Preliminary
 2002 Microchip Technology Inc.
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