PIC18F4539 Datasheet, PDF (151/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
16.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I²C bus may be taken when the
P bit is set or the bus is IDLE, with both the S and P bits
clear.
In Firmware Controlled Master mode, user code con-
ducts all I²C bus operations based on START and
STOP bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I²C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a STOP condition on SDA and SCL.
Note:
The MSSP Module, when configured in I²C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
The following events will cause SSP interrupt flag bit,
SSPIF, to be set (SSP interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated START
FIGURE 16-16: MSSP BLOCK DIAGRAM (I²C MASTER MODE)
Read
Internal
Data Bus
Write
SSPBUF
SDA
SDA in
SSPSR
MSb
Shift
Clock
LSb
SCL
START bit, STOP bit,
Acknowledge
Generate
SSPM3:SSPM0
SSPADD<6:0>
Baud
Rate
Generator
SCL in
Bus Collision
START bit Detect
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 149