PIC18F4539 Datasheet, PDF(181/322 Page) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

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PIC18F4539 Datasheet, PDF (181/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

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PIC18FXX39

17.4 USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the RC6/TX/CK pin (instead of being supplied internally

in Master mode). This allows the device to transfer or

receive data while in SLEEP mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

17.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical, except in the case of the SLEEP

mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will now be

set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

To set up a Synchronous Slave Transmission:

1. Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

2. Clear bits CREN and SREN.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting enable bit

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the TXREG

register.

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

All Other

RESETS

INTCON

GIE/

GIEH

PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF

GIEL

RBIF 0000 000x 0000 000u

PIR1

PSPIF(1) ADIF RCIF TXIF SSPIF

â TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

PSPIE(1) ADIE RCIE TXIE SSPIE

â TMR2IE TMR1IE 0000 0000 0000 0000

IPR1

PSPIP(1) ADIP RCIP TXIP SSPIP

â TMR2IP TMR1IP 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x

TXREG USART Transmit Register

0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC â BRGH TRMT TX9D 0000 -010 0000 -010

SPBRG Baud Rate Generator Register

0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as '0'.

Shaded cells are not used for Synchronous Slave Transmission.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits

clear.

ï£© 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 179

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