PIC18F4539 Datasheet, PDF (38/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
4.3 Fast Register Stack
For PIC18FXX39 devices, a “fast interrupt return”
option is available for high priority interrupts. A single
level Fast Register Stack is provided for the STATUS,
WREG and BSR registers; it is not readable or writable.
When the processor vectors for an interrupt, the stack
is loaded with the current value of the corresponding
register. If the FAST RETURN instruction is used to
return from the interrupt, the values in the registers are
then loaded back into the working registers.
Note:
The fast interrupt return for PIC18FXX39
devices is reserved for use by the ProMPT
kernel and the Timer2 match interrupt. It is
not available to the user for any other
interrupts or returns from subroutines.
4.4 PCL, PCLATH and PCLATU
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ‘0’.
The PC increments by 2 to address sequential
instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1).
4.5 Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-3.
FIGURE 4-3:
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Execute INST (PC-2)
Fetch INST (PC)
PC+2
Execute INST (PC)
Fetch INST (PC+2)
Q1 Q2 Q3 Q4
PC+4
Execute INST (PC+2)
Fetch INST (PC+4)
Internal
Phase
Clock
DS30485A-page 36
Preliminary
 2002 Microchip Technology Inc.