PIC18F4539 Datasheet, PDF (227/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
BTG
Bit Toggle f
Syntax:
[ label ] BTG f,b[,a]
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operation:
(f<b>) → f<b>
Status Affected: None
Encoding:
0111 bbba ffff ffff
Description:
Bit 'b' in data memory location 'f' is
inverted. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [0x75]
After Instruction:
PORTC = 0110 0101 [0x65]
BOV
Branch if Overflow
Syntax:
[ label ] BOV n
Operands:
-128 ≤ n ≤ 127
Operation:
if overflow bit is ‘1’
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1110 0100 nnnn nnnn
Description:
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Decode
Read literal
'n'
No
operation
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
If No Jump:
Q1
Decode
Q2
Read literal
'n'
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Overflow =
PC
=
If Overflow =
PC
=
BOV Jump
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 225