PIC18F4539 Datasheet, PDF (250/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
SUBWFB
Subtract W from f with Borrow
Syntax:
[ label ] SUBWFB f [,d [,a]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Status Affected: N, OV, C, DC, Z
Encoding:
0101 10da ffff ffff
Description:
Subtract W and the carry flag (bor-
row) from register 'f' (2’s complement
method). If 'd' is 0, the result is stored
in W. If 'd' is 1, the result is stored
back in register 'f' (default). If ‘a’ is 0,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is 1,
then the bank will be selected as per
the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Example 1:
SUBWFB REG, 1, 0
Before Instruction
REG = 0x19
W
= 0x0D
C
=1
After Instruction
REG = 0x0C
W
= 0x0D
C
=1
Z
=0
N
=0
(0001 1001)
(0000 1101)
(0000 1011)
(0000 1101)
; result is positive
Example 2:
SUBWFB REG, 0, 0
Before Instruction
REG = 0x1B
W
= 0x1A
C
=0
After Instruction
REG = 0x1B
W
= 0x00
C
=1
Z
=1
N
=0
(0001 1011)
(0001 1010)
(0001 1011)
; result is zero
Example 3:
SUBWFB REG, 1, 0
Before Instruction
REG = 0x03
W
= 0x0E
C
=1
After Instruction
REG = 0xF5
W
= 0x0E
C
=0
Z
=0
N
=1
(0000 0011)
(0000 1101)
(1111 0100)
; [2’s comp]
(0000 1101)
; result is negative
SWAPF
Swap f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
[ label ] SWAPF f [,d [,a]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
None
0011 10da ffff ffff
The upper and lower nibbles of reg-
ister 'f' are exchanged. If 'd' is 0, the
result is placed in W. If 'd' is 1, the
result is placed in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is 1, then the
bank will be selected as per the
BSR value (default).
1
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register 'f'
Q3
Process
Data
Q4
Write to
destination
Example:
SWAPF REG, 1, 0
Before Instruction
REG = 0x53
After Instruction
REG = 0x35
DS30485A-page 248
Preliminary
 2002 Microchip Technology Inc.