PIC18F4539 Datasheet, PDF(218/322 Page) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

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PIC18F4539 Datasheet, PDF (218/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

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PIC18FXX39

TABLE 21-2: PIC18FXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands

Description

Cycles

16-Bit Instruction Word

MSb

LSb

Status

Affected

Notes

LITERAL OPERATIONS

ADDLW k

Add literal and WREG

1

ANDLW k

AND literal with WREG

1

IORLW

k

Inclusive OR literal with WREG

1

LFSR

f, k Move literal (12-bit) 2nd word

2

to FSRx 1st word

MOVLB k

Move literal to BSR<3:0>

1

MOVLW k

Move literal to WREG

1

MULLW k

Multiply literal with WREG

1

RETLW

k

Return with literal in WREG

2

SUBLW k

Subtract WREG from literal

1

XORLW k

Exclusive OR literal with WREG 1

0000

0000

0000

1110

1111

0000

0000

0000

0000

0000

0000

1111

1011

1001

1110

0000

0001

1110

1101

1100

1000

1010

kkkk

kkkk

kkkk

00ff

kkkk

0000

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

kkkk

C, DC, Z, OV, N

Z, N

Z, N

None

None

None

None

None

C, DC, Z, OV, N

Z, N

DATA MEMORY â PROGRAM MEMORY OPERATIONS

TBLRD*

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

2

2 (5)

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

1000

1001

1010

1011

1100

1101

1110

1111

None

None

None

None

None

None

None

None

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an

external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory

locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

DS30485A-page 216

Preliminary

ï£© 2002 Microchip Technology Inc.

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