PIC18F4539 Datasheet, PDF (65/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
6.3 Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>), clear the CFGS control bit
(EECON1<6>), and then set control bit RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation).
EXAMPLE 6-1: DATA EEPROM READ
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, CFGS
EECON1, RD
EEDATA, W
;
; Data Memory Address to read
; Point to DATA memory
; Access program FLASH or Data EEPROM memory
; EEPROM Read
; W = EEDATA
6.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. Then, the sequence in
Example 6-2 must be followed to initiate the write cycle.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADR and EDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. The user may either
enable this interrupt, or poll this bit. EEIF must be
cleared by software.
EXAMPLE 6-2: DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
;
; Data Memory Address to read
;
; Data Memory Value to write
; Point to DATA memory
; Access program FLASH or Data EEPROM memory
; Enable writes
Required
Sequence
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
; Disable interrupts
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Enable interrupts
.
; user code execution
.
.
BCF
EECON1, WREN ; Disable writes on write complete (EEIF set)
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 63