PIC18F4539 Datasheet, PDF (22/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
TABLE 2-1:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Ranges Tested:
Mode
Freq
C1
C2
HS
20.0 MHz 15-33 pF
15-33 pF
These values are for design guidance only.
See notes following this table.
Crystals Used
20.0 MHz Epson CA-301 20.000M-C ± 30 PPM
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: Rs may be required in HS mode to avoid
overdriving crystals with low drive level
specification.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components, or
verify oscillator performance.
2.3 External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from SLEEP mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-3:
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
Clock from
Ext. System
FOSC/4
OSC1
PIC18FXX39
OSC2
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-4 shows the pin connections
for the ECIO Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
Clock from
Ext. System
RA6
OSC1
PIC18FXX39
I/O (OSC2)
2.4 HS/PLL
A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the fre-
quency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 5 MHz, the internal
clock frequency will be multiplied to 20 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes specified by the
FOSC<2:0> configuration bits. The Oscillator mode is
specified during device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
DS30485A-page 20
Preliminary
 2002 Microchip Technology Inc.