PIC18F4539 Datasheet, PDF (317/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
SSPSTAT Register
R/W Bit ............................................................. 138, 139
Status Bits
Significance and the Initialization Condition
for RCON Register ............................................. 25
SUBFWB .......................................................................... 246
SUBLW ............................................................................ 247
SUBWF ............................................................................ 247
SUBWFB .......................................................................... 248
SWAPF ............................................................................ 248
T
TABLAT Register ............................................................... 54
Table Pointer Operations (table) ........................................ 54
TBLPTR Register ............................................................... 54
TBLRD ............................................................................. 249
TBLWT ............................................................................. 250
Time-out Sequence ............................................................ 24
Time-out in Various Sitations ..................................... 25
Timer0 ................................................................................ 99
16-bit Mode Timer Reads and Writes ...................... 101
Associated Registers ............................................... 101
Clock Source Edge Select (T0SE Bit) ...................... 101
Clock Source Select (T0CS Bit) ............................... 101
Operation ................................................................. 101
Overflow Interrupt .................................................... 101
Prescaler. See Prescaler, Timer0
Timer1 .............................................................................. 103
16-bit Read/Write Mode ........................................... 105
Associated Registers ............................................... 105
Operation ................................................................. 104
Oscillator .................................................................. 103
Overflow Interrupt ............................................ 103, 105
TMR1H Register ...................................................... 103
TMR1L Register ....................................................... 103
Timer2 .............................................................................. 107
TMR2 to PR2 Match Interrupt .................................. 123
Timer3 .............................................................................. 109
Associated Registers ............................................... 111
Operation ................................................................. 110
Oscillator .................................................................. 109
Overflow Interrupt ............................................ 109, 111
TMR3H Register ...................................................... 109
TMR3L Register ....................................................... 109
Timing Diagrams
A/D Conversion ........................................................ 285
Acknowledge Sequence .......................................... 158
Asynchronous Reception ......................................... 175
Asynchronous Transmission .................................... 173
Asynchronous Transmission (Back to Back) ........... 173
Baud Rate Generator with Clock Arbitration ............ 152
BRG Reset Due to SDA Arbitration
During START Condition ................................. 161
Brown-out Reset (BOR) ........................................... 272
Bus Collision During a STOP Condition
(Case 1) ........................................................... 163
Bus Collision During a STOP Condition
(Case 2) ........................................................... 163
Bus Collision During Repeated START
Condition (Case 1) ........................................... 162
Bus Collision During Repeated START
Condition (Case 2) ........................................... 162
Bus Collision During START Condition
(SCL = 0) ......................................................... 161
Bus Collision During Start Condition
(SDA Only) ....................................................... 160
Bus Collision for Transmit and Acknowledge ........... 159
CLKO and I/O .......................................................... 271
Clock Synchronization ............................................. 145
Clock/Instruction Cycle .............................................. 36
Example SPI Master Mode (CKE = 0) ..................... 276
Example SPI Master Mode (CKE = 1) ..................... 277
Example SPI Slave Mode (CKE = 0) ....................... 278
Example SPI Slave Mode (CKE = 1) ....................... 279
External Clock (All Modes except PLL) ................... 270
First START Bit Timing ............................................ 153
I²C Bus Data ............................................................ 280
I²C Bus START/STOP Bits ...................................... 280
I²C Master Mode (7 or 10-bit Transmission) ............ 156
I²C Master Mode (7-bit Reception) .......................... 157
I²C Slave Mode (10-bit Transmission) ..................... 143
I²C Slave Mode (7-bit Transmission) ....................... 141
I²C Slave Mode with SEN = 0
(10-bit Reception) ............................................ 142
I²C Slave Mode with SEN = 0
(7-bit Reception) .............................................. 140
I²C Slave Mode with SEN = 1
(10-bit Reception) ............................................ 147
I²C Slave Mode with SEN = 1
(7-bit Reception) .............................................. 146
Low Voltage Detect ................................................. 192
Master SSP I²C Bus Data ........................................ 282
Master SSP I²C Bus START/STOP Bits .................. 282
Parallel Slave Port (PIC18F4X39) ........................... 275
Parallel Slave Port (Read) ......................................... 97
Parallel Slave Port (Write) ......................................... 96
PWM (PWM1 and PWM2) ....................................... 274
PWM Output ............................................................ 123
Repeat START Condition ........................................ 154
RESET, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 272
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) .............................. 148
Slave Synchronization ............................................. 131
Slow Rise Time (MCLR Tied to VDD) ......................... 31
SPI Mode (Master Mode) ......................................... 130
SPI Mode (Slave Mode with CKE = 0) ..................... 132
SPI Mode (Slave Mode with CKE = 1) ..................... 132
Stop Condition Receive or Transmit Mode .............. 158
Synchronous Reception (Master Mode, SREN) ...... 178
Synchronous Transmission ..................................... 177
Synchronous Transmission (Through TXEN) .......... 177
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) .......................................... 31
Time-out Sequence on Power-up
(MCLR Not Tied to VDD)
Case 1 ............................................................... 30
Case 2 ............................................................... 30
Time-out Sequence on Power-up
(MCLR Tied to VDD) .......................................... 30
Timer0 and Timer1 External Clock .......................... 273
USART Synchronous Receive (Master/Slave) ........ 284
USART Synchronous Transmission
(Master/Slave) ................................................. 284
Wake-up from SLEEP via Interrupt .......................... 206
Timing Diagrams Requirements
Master SSP I²C Bus START/STOP Bits .................. 282
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 315