PIC18F4539 Datasheet, PDF (75/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
REGISTER 8-3:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON3 REGISTER
R/W-1 R/W-1
U-0
R/W-0 R/W-0
U-0
R/W-0
INT2IP⁽¹⁾ INT1IP⁽¹⁾
—
INT2IE INT1IE
—
INT2IF
bit 7
INT2IP⁽¹⁾: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
INT1IP⁽¹⁾: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as '0'
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
Unimplemented: Read as '0'
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note 1: Maintain this bit cleared (= 0).
R/W-0
INT1IF
bit 0
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 73