PIC18F4539 Datasheet, PDF (31/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
IPR2
2439 4439 2539 4539 ---1 1111
---1 1111
---u uuuu
PIR2
2439 4439 2539 4539 ---0 0000
---0 0000
---u uuuu⁽³⁾
PIE2
2439 4439 2539 4539 ---0 0000
---0 0000
---u uuuu
IPR1
2439 4439 2539 4539
2439 4439 2539 4539
1111 1111
-111 1111
1111 1111
-111 1111
uuuu uuuu
-uuu uuuu
PIR1
2439 4439 2539 4539
2439 4439 2539 4539
0000 0000
-000 0000
0000 0000
-000 0000
uuuu uuuu⁽³⁾
-uuu uuuu⁽³⁾
PIE1
2439 4439 2539 4539
2439 4439 2539 4539
0000 0000
-000 0000
0000 0000
-000 0000
uuuu uuuu
-uuu uuuu
TRISE
2439 4439 2539 4539 0000 -111
0000 -111
uuuu -uuu
TRISD
2439 4439 2539 4539 1111 1111
1111 1111
uuuu uuuu
TRISC*
2439 4439 2539 4539 1111 1111
1111 1111
uuuu uuuu
TRISB
2439 4439 2539 4539 1111 1111
1111 1111
uuuu uuuu
TRISA^(5,6) 2439 4439 2539 4539
-111 1111⁽⁵⁾
-111 1111⁽⁵⁾
-uuu uuuu⁽⁵⁾
LATE
2439 4439 2539 4539 ---- -xxx
---- -uuu
---- -uuu
LATD
2439 4439 2539 4539 xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC*
2439 4439 2539 4539 xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
2439 4439 2539 4539 xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA^(5,6)
2439 4439 2539 4539
-xxx xxxx⁽⁵⁾
-uuu uuuu⁽⁵⁾
-uuu uuuu⁽⁵⁾
PORTE
2439 4439 2539 4539 ---- -000
---- -000
---- -uuu
PORTD
2439 4439 2539 4539 xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC*
2439 4439 2539 4539 xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
2439 4439 2539 4539 xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA^(5,6) 2439 4439 2539 4539
-x0x 0000⁽⁵⁾
-u0u 0000⁽⁵⁾
-uuu uuuu⁽⁵⁾
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits
are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 29