PIC18F4539 Datasheet, PDF (135/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

PIC18FXX39
16.3.8 SLEEP OPERATION
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from SLEEP.
16.3.9 EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
16.3.10 BUS MODE COMPATIBILITY
Table 16-1 shows the compatibility between the
standard SPI modes and the states the CKP and CKE
control bits.
TABLE 16-1: SPI BUS MODES
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
1
0
0
1
1
1
0
There is also an SMP bit which controls when the data
is sampled.
TABLE 16-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
RESETS
INTCON
GIE/GIEH PEIE/ TMR0IE INT0IE
GIEL
RBIE
TMR0IF INT0IF
RBIF 0000 000x 0000 000u
PIR1
PSPIF⁽¹⁾ ADIF
RCIF
TXIF
SSPIF
—
TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
IPR1
PSPIE⁽¹⁾
PSPIP⁽¹⁾
ADIE
ADIP
RCIE
RCIP
TXIE
TXIP
SSPIE
SSPIP
—
TMR2IE TMR1IE 0000 0000 0000 0000
—
TMR2IP TMR1IP 0000 0000 0000 0000
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3
*
*
TRISC0 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
SSPCON
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA
—
PORTA Data Direction Register
-111 1111 -111 1111
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.
* Reserved bits; do not modify.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear.
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 133