PIC18F4539 Datasheet, PDF (69/322 Pages) Microchip Technology – Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel

7.0 8 X 8 HARDWARE MULTIPLIER
7.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX39 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 7-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
PIC18FXX39
7.2 Operation
Example 7-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 7-1:
MOVF ARG1, W
MULWF ARG2
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 7-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
TABLE 7-1: PERFORMANCE COMPARISON
Routine
Multiply Method
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
Program
Memory
(Words)
13
1
33
6
21
28
52
35
Cycles
(Max)
69
1
91
6
242
28
254
40
Time
@ 40 MHz
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.8 µs
25.4 µs
4.0 µs
@ 10 MHz
27.6 µs
400 ns
36.4 µs
2.4 µs
96.8 µs
11.2 µs
102.6 µs
16.0 µs
@ 4 MHz
69 µs
1 µs
91 µs
6 µs
242 µs
28 µs
254 µs
40 µs
 2002 Microchip Technology Inc.
Preliminary
DS30485A-page 67