PIC18F2585_07 Datasheet, PDF (83/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2585/2680/4585/4680) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TXB1SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16 xxx- x-xx 54, 283
TXB1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 54, 283
TXB1CON
TXBIF
TXABT TXLARB TXERR
TXREQ
—
TXPRI1
TXPRI0 0000 0-00 54, 282
TXB2D7
TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 54, 284
TXB2D6
TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 xxxx xxxx 54, 284
TXB2D5
TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 xxxx xxxx 54, 284
TXB2D4
TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 xxxx xxxx 54, 284
TXB2D3
TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 xxxx xxxx 54, 284
TXB2D2
TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 xxxx xxxx 54, 284
TXB2D1
TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 xxxx xxxx 55, 284
TXB2D0
TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 xxxx xxxx 55, 284
TXB2DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0 -x-- xxxx 55, 285
TXB2EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 55, 284
TXB2EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 55, 283
TXB2SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16 xxxx x-xx 55, 283
TXB2SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxx- x-xx 55, 283
TXB2CON
TXBIF
TXABT TXLARB TXERR
TXREQ
—
TXPRI1
TXPRI0 0000 0-00 55, 282
RXM1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 55, 304
RXM1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 55, 304
RXM1SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16 xxx- x-xx 55, 304
RXM1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 55, 304
RXM0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 55, 304
RXM0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 55, 304
RXM0SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16 xxx- x-xx 55, 304
RXM0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 55, 303
RXF5EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 55, 303
RXF5EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 55, 303
RXF5SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16 xxx- x-xx 55, 302
RXF5SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 55, 302
RXF4EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 55, 303
RXF4EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 55, 303
RXF4SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16 xxx- x-xx 55, 302
RXF4SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 55, 302
RXF3EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 55, 303
RXF3EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 55, 303
RXF3SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16 xxx- x-xx 55, 302
RXF3SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 55, 302
RXF2EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 55, 303
RXF2EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 55, 303
RXF2SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16 xxx- x-xx 55, 302
RXF2SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 55, 302
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X8X devices and are read as ‘0’. Reset values are shown for PIC18F4X8X
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X8X devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 81