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| PIC18F2585_07 Datasheet, PDF (147/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology | |||
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PIC18F2585/2680/4585/4680
FIGURE 10-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-4:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTD(1)
LATD(1)
TRISD(1)
PORTE(1)
LATE(1)
TRISE(1)
RD7
RD6
RD5
RD4
RD3
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Control Register
â
â
â
â
RE3
â
â
â
â
â
IBF
OBF
IBOV PSPMODE
â
RD2
RD1
RE2
RE1
LATE Data Output bits
TRISE2 TRISE1
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PSPIF(2)
PSPIE(2)
PSPIP(2)
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RCIF
RCIE
RCIP
INT0IE
TXIF
TXIE
TXIP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
ADCON1
â
CMCON(1) C2OUT
â
C1OUT
VCFG1
C2INV
VCFG0
C1INV
PCFG3
CIS
PCFG2
CM2
PCFG1
CM1
Legend: â = unimplemented, read as â0â. Shaded cells are not used by the Parallel Slave Port.
Note 1: These registers are available on PIC18F4X8X devices only.
2: These registers are unimplemented on PIC18F2X8X devices and read as â0â.
Bit 0
RD0
RE0
TRISE0
RBIF
TMR1IF
TMR1IE
TMR1IP
PCFG0
CM0
Reset
Values
on page
52
52
52
52
52
52
49
52
52
52
50
51
© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 145
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