PIC18F2585_07 Datasheet, PDF (80/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2585/2680/4585/4680) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
SPBRGH
EUSART Baud Rate Generator High Byte
0000 0000 51, 231
SPBRG
EUSART Baud Rate Generator
0000 0000 51, 231
RCREG
EUSART Receive Register
0000 0000 51, 238
TXREG
EUSART Transmit Register
0000 0000 51, 236
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 51, 237
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 51, 237
EEADRH
—
—
—
—
—
—
EEPROM Addr Register High ---- --00 51, 108
EEADR
EEPROM Address Register
0000 0000 51, 105
EEDATA
EEPROM Data Register
0000 0000 51, 105
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000 51, 105
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 51, 105
IPR3
Mode 0
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP 1111 1111 51, 126
IPR3
Mode 1, 2
IRXIP
WAKIP
ERRIP
TXBnIP _TXB1IP(8) _TXB0IP(8)
RXBnIP FIFOWMIP 1111 1111 51, 126
PIR3
Mode 0
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF 0000 0000 51, 120
PIR3
Mode 1, 2
IRXIF
WAKIF
ERRIF
TXBnIF _TXB1IF(8) _TXB0IF(8)
RXBnIF FIFOWMIF 0000 0000 51, 120
PIE3
Mode 0
IRXIE
WAKIE
ERRIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE 0000 0000 51, 123
PIE3
Mode 1, 2
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE⁽³⁾
TRISD⁽³⁾
IRXIE
WAKIE
ERRIE
TXBnIE _TXB1IE(8)
OSCFIP
OSCFIF
OSCFIE
PSPIP⁽³⁾
PSPIF⁽³⁾
PSPIE⁽³⁾
INTSRC
CMIP⁽⁹⁾
CMIF⁽⁹⁾
CMIE⁽⁹⁾
ADIP
ADIF
ADIE
PLLEN⁽⁴⁾
—
—
—
RCIP
RCIF
RCIE
—
EEIP
EEIF
EEIE
TXIP
TXIF
TXIE
TUN4
IBF
OBF
IBOV PSPMODE
Data Direction Control Register for PORTD
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
TXB0IE⁽⁸⁾
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
TRISE2
RXBnIE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
TRISE1
FIFOMWIE 0000 0000 51, 123
ECCP1IP⁽⁹⁾
ECCP1IF⁽⁹⁾
ECCP1IE⁽⁹⁾
11-1 1111
00-0 0000
00-0 0000
51, 125
51, 119
52, 122
TMR1IP 1111 1111 52, 124
TMR1IF 0000 0000 52, 118
TMR1IE 0000 0000 52, 121
TUN0 0q-0 0000 27, 52
TRISE0 0000 -111 52, 141
1111 1111 52, 138
TRISC
Data Direction Control Register for PORTC
1111 1111 52, 135
TRISB
TRISA
LATE⁽³⁾
LATD⁽³⁾
Data Direction Control Register for PORTB
TRISA7⁽⁶⁾ TRISA6⁽⁶⁾ Data Direction Control Register for PORTA
—
—
—
—
—
LATE2
Read PORTD Data Latch, Write PORTD Data Latch
LATE1
LATE0
1111 1111 52, 132
1111 1111 52, 129
---- -xxx 52, 141
xxxx xxxx 52, 138
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx 52, 135
LATB
LATA
Read PORTB Data Latch, Write PORTB Data Latch
LATA7⁽⁶⁾ LATA6⁽⁶⁾ Read PORTA Data Latch, Write PORTA Data Latch
xxxx xxxx 52, 132
xxxx xxxx 52, 129
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X8X devices and are read as ‘0’. Reset values are shown for PIC18F4X8X
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X8X devices only.
DS39625C-page 78
Preliminary
© 2007 Microchip Technology Inc.