PIC18F2585_07 Datasheet, PDF (126/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
9.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1, IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 9-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP⁽¹⁾
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
CCP1IP
bit 7
R/W-1
TMR2IP
R/W-1
TMR1IP
bit 0
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit⁽¹⁾
1 = High priority
0 = Low priority
Note 1: This bit is reserved on PIC18F2X8X devices; always maintain this bit set.
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39625C-page 124
Preliminary
© 2007 Microchip Technology Inc.