PIC18F2585_07 Datasheet, PDF (52/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
BSR
2585 2680 4585 4680 ---- 0000
---- 0000
---- uuuu
INDF2
2585 2680 4585 4680
N/A
N/A
N/A
POSTINC2 2585 2680 4585 4680
N/A
N/A
N/A
POSTDEC2 2585 2680 4585 4680
N/A
N/A
N/A
PREINC2
2585 2680 4585 4680
N/A
N/A
N/A
PLUSW2
2585 2680 4585 4680
N/A
N/A
N/A
FSR2H
2585 2680 4585 4680 ---- 0000
---- 0000
---- uuuu
FSR2L
2585 2680 4585 4680 xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
2585 2680 4585 4680 ---x xxxx
---u uuuu
---u uuuu
TMR0H
2585 2680 4585 4680 0000 0000
0000 0000
uuuu uuuu
TMR0L
2585 2680 4585 4680 xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
2585 2680 4585 4680 1111 1111
1111 1111
uuuu uuuu
OSCCON
2585 2680 4585 4680 0100 q000
0100 00q0
uuuu uuqu
HLVDCON 2585 2680 4585 4680 0-00 0101
0-00 0101
0-uu uuuu
WDTCON
RCON⁽⁴⁾
2585 2680 4585 4680
2585 2680 4585 4680
---- ---0
0q-1 11q0
---- ---0
0q-q qquu
---- ---u
uq-u qquu
TMR1H
2585 2680 4585 4680 xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
2585 2680 4585 4680 xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
2585 2680 4585 4680 0000 0000
u0uu uuuu
uuuu uuuu
TMR2
2585 2680 4585 4680 0000 0000
0000 0000
uuuu uuuu
PR2
2585 2680 4585 4680 1111 1111
1111 1111
1111 1111
T2CON
2585 2680 4585 4680 -000 0000
-000 0000
-uuu uuuu
SSPBUF
2585 2680 4585 4680 xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
2585 2680 4585 4680 0000 0000
0000 0000
uuuu uuuu
SSPSTAT
2585 2680 4585 4680 0000 0000
0000 0000
uuuu uuuu
SSPCON1 2585 2680 4585 4680 0000 0000
0000 0000
uuuu uuuu
SSPCON2 2585 2680 4585 4680 0000 0000
0000 0000
uuuu uuuu
ADRESH
2585 2680 4585 4680 xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
2585 2680 4585 4680 xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
2585 2680 4585 4680 --00 0000
--00 0000
--uu uuuu
ADCON1
2585 2680 4585 4680 --00 0qqq
--00 0qqq
--uu uuuu
ADCON2
2585 2680 4585 4680 0-00 0000
0-00 0000
u-uu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
DS39625C-page 50
Preliminary
© 2007 Microchip Technology Inc.