PIC18F2585_07 Datasheet, PDF (377/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
BTG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Toggle f
BTG f, b {,a}
0 ≤ f ≤ 255
0≤b<7
a ∈ [0,1]
(f<b>) → f<b>
None
0111 bbba ffff ffff
Bit ‘b’ in data memory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC =
After Instruction:
PORTC =
0111 0101 [75h]
0110 0101 [65h]
BOV
Branch if Overflow
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
BOV n
-128 ≤ n ≤ 127
if Overflow bit is ‘1’
(PC) + 2 + 2n → PC
None
1110 0100 nnnn nnnn
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
‘n’
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Overflow =
PC
=
If Overflow =
PC
=
BOV Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 375