PIC18F2585_07 Datasheet, PDF (169/482 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
15.3 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (ECCP1M3:ECCP1M0). At the same time,
the interrupt flag bit ECCP1IF is set.
15.3.1 CCP1 PIN CONFIGURATION
The user must configure the CCP1 (ECCP1) pin as an
output by clearing the appropriate TRIS bit.
Note:
Clearing the CCP1CON register will force
the RC2 compare output latch (depending
on device configuration) to the default low
level. This is not the PORTC I/O data
latch.
15.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP1 module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCP1M3:CCP1M0 = 1010), the CCP1 pin is not
affected. Only a CCP1 interrupt is generated, if enabled
and the CCP1IE bit is set.
15.3.4 SPECIAL EVENT TRIGGER
Both CCP1 modules are equipped with a special event
trigger. This is an internal hardware signal generated in
Compare mode to trigger actions by other modules.
The special event trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP1M3:CCP1M0 = 1011).
For either CCP1 module, the special event trigger
resets the timer register pair for whichever timer
resource is currently assigned as the module’s time
base. This allows the CCPR1 (ECCPR1) registers to
serve as a programmable period register for either
timer.
FIGURE 15-2:
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR1H CCPR1L
Set CCP1IF
Comparator
Compare
Match
TMR1H TMR1L
0
Special Event Trigger
(Timer1 Reset)
Output
Logic
4
CCP1CON<3:0>
SQ
R
CCP1 pin
TRIS
Output Enable
TMR3H TMR3L
T3CCP1
1
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
T3ECCP1
Set CCP1IF
Comparator
Compare
Match
Output
Logic
SQ
R
ECCPR1H ECCPR1L
4
ECCP1CON<3:0>
ECCP1 pin
TRIS
Output Enable
© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 167